Optimization of Spin-Transfer Torque Magnetic Tunnel Junction-Based Logic Gates

By offering zero standby power, non-volatile logic is a promising solution to overcome the leakage losses which have become an important obstacle to scaling of CMOS technology [1]. Magnetic tunnel junctions (MTJs) offer a great potential, because of their unlimited endurance, CMOS compatibility, and fast switching speed. Recently, several realizations of MTJ-based logic gates have been demonstrated using spin-transfer torque (STT) MTJs for which the MTJ devices are used simultaneously as memory and logic gates [2], [3]. This intrinsically enables logic-in-memory architectures with no need for extra hardware [4]. The error probabilities in these gates depend significantly on device and circuit parameters. Here, we present a method to optimize the device and circuit parameters by minimizing the errors.